#define SYS_TMM_MCU_SHARED_MEM_OFFSET_ADDR 0x1fc00

#define SYS_TMM_MCU_RAM_MEM_ADDR_0 0x62400000
#define SYS_TMM_MCU_RAM_MEM_ADDR_1 0x62480000
#define SYS_TMM_MCU_RAM_MEM_ADDR_2 0x61000000
#define SYS_TMM_MCU_RAM_MEM_ADDR_3 0x6a400000
#define SYS_TMM_MCU_RAM_MEM_ADDR_4 0x6a480000
#define SYS_TMM_MCU_RAM_MEM_ADDR_5 0x69000000
#define SYS_TMM_MCU_RAM_MEM_ADDR_6 0x55480000

#define SYS_TMM_MCU_SHARED_MEM_BASE_ADDR_0 0x6241fc00
#define SYS_TMM_MCU_SHARED_MEM_BASE_ADDR_1 0x6249fc00
#define SYS_TMM_MCU_SHARED_MEM_BASE_ADDR_2 0x6101fc00
#define SYS_TMM_MCU_SHARED_MEM_BASE_ADDR_3 0x6a41fc00
#define SYS_TMM_MCU_SHARED_MEM_BASE_ADDR_4 0x6a49fc00
#define SYS_TMM_MCU_SHARED_MEM_BASE_ADDR_5 0x6901fc00
#define SYS_TMM_MCU_SHARED_MEM_BASE_ADDR_6 0x5549fc00

#define SYS_TMM_MCU_SERDES_FW_ANCHOR_0 0x6240fc00
#define SYS_TMM_MCU_SERDES_FW_ANCHOR_1 0x6248fc00
#define SYS_TMM_MCU_SERDES_FW_ANCHOR_2 0x6100fc00
#define SYS_TMM_MCU_SERDES_FW_ANCHOR_3 0x6a40fc00
#define SYS_TMM_MCU_SERDES_FW_ANCHOR_4 0x6a48fc00
#define SYS_TMM_MCU_SERDES_FW_ANCHOR_5 0x6900fc00
#define SYS_TMM_MCU_SERDES_FW_ANCHOR_6 0x5548fc00


#define GLB_INFO_MCU_ID                  0x00
#define GLB_INFO_LOAD_OK_IND             0x04
#define GLB_INFO_LOAD_ERR_IND            0x08
#define GLB_INFO_LOAD_STATUS             0x0c
#define GLB_INFO_REG_ALL_DELAY_US        0x10
#define GLB_INFO_STEP0_DELAY_US          0x14
#define GLB_INFO_FLEXE_CMD_CODE          0x20   /*[31, 24] : cs_id, [23, 16] : pcs_chan_bmp, [15, 8] : work_mode, [7, 0] : enable*/
#define GLB_INFO_FLEXE_CMD_STATUS        0x24
#define GLB_INFO_FLEXE_CMD_RESULT        0x28
#define GLB_INFO_SW_MODE                 0x2c
#define GLB_INFO_FLEXE_ADJUST_SWITCH     0x30  
#define GLB_INFO_TMM_LOAD_FW_SWITCH      0x34
#define GLB_INFO_OCTAL_SERDES_EN         0x38
#define GLB_INFO_FLEXE_PADDING_CMD_STATUS 0x3c
#define GLB_INFO_DBG_ADDR_5              0x74
#define GLB_INFO_DBG_ADDR_6              0x78
#define GLB_INFO_DBG_ADDR_7              0x7c
#define GLB_INFO_DBG_ADDR_8              0x80
#define GLB_INFO_DBG_ADDR_15             0x9c


#define SYS_TMM_MCU_NUM                7

#define SYS_TMM_HSS_ID_TO_MCU_ID(hss_id, mcu_id)   (mcu_id = (hss_id / 2));

enum sys_tmm_mcu_flexe_cmd_status_e
{
    SYS_MCU_FLEXE_CMD_STATUS_DOING = 0,    
    SYS_MCU_FLEXE_CMD_STATUS_DONE,
    SYS_MCU_FLEXE_CMD_STATUS_TIME_OUT,
    SYS_MCU_FLEXE_CMD_STATUS_FAIL,
    SYS_MCU_FLEXE_CMD_STATUS_MAX
};
typedef enum sys_tmm_mcu_flexe_cmd_status_e sys_tmm_mcu_flexe_cmd_status_t;

enum sys_tmm_mcu_flexe_cmd_enable_e
{
    SYS_MCU_FLEXE_CMD_ENABLE_NOTHING = 0,       /*do nothing*/
    SYS_MCU_FLEXE_CMD_ENABLE_RD_ADJ,            /*read buffer depth and adjust buffer depth*/
    SYS_MCU_FLEXE_CMD_ENABLE_ONLY_RD,           /*only read buffer depth*/
    SYS_MCU_FLEXE_CMD_ENABLE_RD_STATS,          /*read buffer depth and statistics buffer minimum value*/
    SYS_MCU_FLEXE_CMD_ENABLE_PAD_CFG,           /* padding cfg*/
    SYS_MCU_FLEXE_CMD_ENABLE_MAX
};
typedef enum sys_tmm_mcu_flexe_cmd_enable_e sys_tmm_mcu_flexe_cmd_enable_t;

enum sys_tmm_mcu_flexe_cmd_wk_mode_e
{
    SYS_MCU_FLEXE_CMD_WK_MODE_NONE_RS528 = 0,  
    SYS_MCU_FLEXE_CMD_WK_MODE_RS544,      
    SYS_MCU_FLEXE_CMD_WK_MOD_MAX
};
typedef enum sys_tmm_mcu_flexe_cmd_wk_mode_e sys_tmm_mcu_flexe_cmd_wk_mode_t;

enum sys_tmm_mcu_sw_mode_e
{
    IDLE_MODE   = 0, 
    NORMAL_MODE = 1,  
    FLEXE_ADJ_MODE   = 2, 
    SW_MODE_BUTT
};
typedef enum sys_tmm_mcu_sw_mode_e sys_tmm_mcu_sw_mode_t;


int32 sys_tmm_mcu_read_shared_memory(uint8 lchip, uint8 mcu_id, uint32 addr, uint32 mask, uint32 *data);
int32 sys_tmm_mcu_write_shared_memory(uint8 lchip, uint8 mcu_id, uint32 addr, uint32 mask, uint32 data);
int32 sys_tmm_mcu_init(uint8 lchip, uint32 mcu_id, uint8 hss_iddq_flag[]);
int32 sys_tmm_mcu_reset_core(uint8 lchip, uint32 mcu_id, uint8 reset);

